This invention relates to an amplifier and, more particularly, to an amplifier using a field effect transistor which is adapted to respond rapidly to a pulse signal, such as a pulse width modulated signal, or other rectangular wave signal.
Amplifier circuits for use with pulse signals should be capable of responding rapidly to the supplied pulse signal. Thus, if a bipolar transistor is used, there should be minimal delay in turning the transistor ON and OFF so that the amplified pulse signal appears as a rectangular waveform having sharp leading and trailing edges. Because of minority carriers which are stored in the base region when a bipolar transistor is in saturation, a delay will elapse until these stored carriers are sufficiently discharged so that the transistor can be turned OFF.
Another problem encountered in pulse amplifiers using bipolar transistors is longitudinal amplitude distortion in the output voltage. This distortion may occur when bipolar transistors are connected in push-pull relation. As described in our U.S. Pat. No. 3,999,143, such longitudinal amplitude distortion can be eliminated if a pair of diodes is connected between the base electrode of one of the push-pull transistors and the usual reverse current by-pass diode that is provided in the event that the load is a loudspeaker system supplied through a choke coil.
While the circuit described in the aforementioned patent operates satisfactorily, a different problem arises when field effect transistors (FET's) are used. Since the FET does not rely on storage carriers for its operation, there is no need to discharge stored carriers in order to turn the FET OFF, as in the case of a bipolar transistor. However, the depletion-type FET, such as a junction FET, and particularly a vertical channel junction FET exhibits inherent input gate capacitance which varies as a function of the gate-source voltage. This gate capacitance cooperates with the output impedance of the drive circuit normally used with the FET to impart a time delay in the turning ON and turning OFF of the FET. This delay is a detriment to the operation of the FET in a pulse amplifying circuit, particularly since this delay can result in rounded leading and trailing edges of the amplified pulse.
Accordingly, it is desirable to drive an FET having inherent input gate capacitance with a circuit of low output impedance. This serves to minimize the RC time delay due to the input gate capacitance of the FET. However, since this input gate capacitance varies as a function of the gate-source voltage, the input gate capacitance tends to increase remarkably when the gate-source circuit of the FET is forward biased. For example, in a N-channel FET, a negative gate-source voltage is effective to turn the FET OFF, and the FET is turned ON when the negative gate-source voltage decreases to a level which forward-biases the gate-source circuit. If the forward bias voltage applied to the gate-source circuit of the N-channel FET becomes positive, the voltage-dependent input gate capacitance thereof increases substantially. This large increase in the input gate capacitance means that an increased amount of power is needed to drive the FET. Furthermore, the drain-source resistance of the transistor when the gate-source voltage is positive is much greater than when a zero forward bias voltage or a low level negative forward bias voltage is applied. This high source-drain resistance means that a significant amount of input power is lost thereby.
Bias voltages of opposite polarities have similar effects upon a P-channel FET. That is, a positive voltage is used to turn OFF the P-channel FET, and the forward bias region is reached when the gate-source voltage is reduced to a low positive level.
As a numerical example, the FET will be forward biased when a gate-source voltage of 0.7 volts (negative for a N-channel FET and positive for a P-channel FET) is applied. As this gate-source voltage is reduced, the input gate capacitance increases remarkably. At zero gate-source voltage a substantial increase in input power is needed. This condition is further aggrevated when the forward bias voltage is increased above zero for the N-channel FET and decreased below zero for the P-channel FET.
In our U.S. Pat. No. 4,021,748, an FET pulse amplifier is described which includes a circuit to prevent the FET from being over-biased in the forward direction. However, in that circuit, a simple diode is connected in parallel with the gate-source circuit. This limits the forward gate-source voltage to, for example, 0.7 volts. As mentioned above, this positive forward bias voltage applied to the gate-source circuit of a N-channel FET results in such a large input gate capacitance as to require a significant amount of power for driving the FET and the load coupled thereto.